Flip-chip assembly technology is widely utilized in semiconductor packaging due to its preferable interconnects between flip-chip dies and laminate, which eliminates the space needed for wire bonding and die surface area of a package and essentially reduces the overall size of the package. In addition, the elimination of wire connections and implementation of shorter electrical paths from the flip-chip dies to the laminate reduce undesired inductance and capacitance.
In recent decades, silicon on insulator (SOI) substrates have been widely used in forming flip-chip dies due to the low cost of silicon materials, large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. However, a thick silicon handle layer in the SOI substrates severely limits the SOI's usage in optical/thermal detecting applications. By using SOI substrates in optical/thermal applications, the thick silicon handle layer will attenuate or obstruct light/thermal signals passing towards optical/thermal sensors, which are integrated in a device layer underlying the thick silicon handle layer. Such attenuation or obstruction of the light/thermal signals causes a slow response and low efficiency of the optical/thermal sensors.
Accordingly, there remains a need for improved microelectronics package designs that improve the response speed and efficiency of the optical/thermal sensors and utilize the advantages of flip-chip assembly. In addition, there is also a need to enhance the performance of the microelectronics package without increasing the package size.